This invention relates to a method of selecting successive columns in successive memory blocks in a serial access memory.
An example of a serial access memory is a first-in-first-out (FIFO) memory that stores serial input data in synchronization with a write clock, and provides the same data in the same order as serial output in synchronization with a read clock. Such memories are often used as line memories or frame memories in image-processing apparatus. The memory stores data in a row-and-column array of memory cells. In access to a given row, successive columns in that row are selected by shifting a pulse through a shift register clocked by the read or write clock. The shift register is configured as a ring counter, so that it repeatedly selects all columns in ascending order.
If the memory capacity is large, practical design considerations require the array to be subdivided into blocks, each block having its own shift registers for read and write access. The shift register design must now be modified, because each row extends through a plurality of blocks. The conventional modification connects the output end of each shift register to the input end of the shift register in the next block, so that a plurality of shift registers form a single ring counter. This leads, however, to two problems.
One problem is that, especially when the number of blocks is large, highly contorted wiring schemes are needed to interconnect the shift registers for read access into one ring and the shift registers for write access into another ring. Another problem is that the interconnecting signal lines become so long that their parasitic resistance and capacitance slows down the operation of the memory, setting an undesirably low maximum frequency on the read clock and write clock and limiting the serial access rate.